1. Field of Invention
The present invention is related to semiconductor memory and more particular non-volatile NAND memory arrays.
2. Description of Related Art
In F. Masuoka et al., xe2x80x9cA New NAND Cell for Ultra High Density 5V-only EEPROMsxe2x80x9d, May 1988, Proc 1988 Symposium on VLSI Technology, IV-5 pp33-34) a floating gate NAND cell, shown in FIG. 1A of prior art, is described that has been used widely as Non-volatile memory. Since the memory cell is placed in series without any contact, the density is very high even though the process complexity is high and the read current level is very small. The storage element in the flash NAND is a polysilicon floating gate 200 residing under a word line 201 in the example shown in FIG. 1A. The floating gate can be replaced by a nitride layer sandwiched between bottom and top oxide layers (Oxide-Nitride-Oxide) 202 laying under a word gate 201 as shown in the example in FIG. 1B and FIG. 1C of prior art. The ONO layer sandwich stores electron or hole charges in the nitride or interface trap sites as suggested in Y. Hayashi et al. xe2x80x9cNonvolatile Semiconductor memory and its Programming Methodxe2x80x9d, JP 11-22940, Dec. 5, 1997. This ONO storage approach for the MONOS NAND simplifies the process significantly compared to the floating gate approach. The floating gate NAND utilizes multi-level storage and provides density factor at least 2 times, whereas a the twin MONOS device of the present invention improves density by storing charges on both device edges in a single planar FET devices. In U.S. Pat. No. 5,768,192 (Eitan) a non-volatile semiconductor memory cell utilizing asymmetrical charge trapping is disclosed. However, the memory cell device suffers from a threshold shift after many program and erase cycles because the electron mean free path is larger than hole mean free path. In U.S. Pat. No. 4,943,943 (Hayashi et al.) a read-out circuit for a semiconductor nonvolatile memory is described which is capable of extracting a widely fluctuating output voltage using a reverse read.
In the present invention, the nitride storage element under the word gate is very small and well defined so that the hole injection for program is applicable over the whole nitride storage region. Erase is achieved by FN (Fowler-Norheim) electron injection, and once the nitride region is limited and optimized, then the voltage required for hole injection can be almost halved. By introducing a trap free oxide region between the two nitride storage sites, the threshold instability from program and erase cycles due to the miss match of hole and electron mean free paths is solved assuring high endurance. The voltage reduction in FN injection is achieved by reducing nitride thickness down to few atomic layers. Thus a low voltage and high density operation is achieved for the MONOS NAND structure of the present invention.
It is an objective of the present invention to provide a twin MONOS memory cell where the two storage sites are beneath a word gate.
It is another objective of the present invention to couple cells in a column together with diffusions located between memory cells.
It is still another objective to isolate cells between columns with a shallow trench isolation.
It is also another objective of the present invention to use the twin MONOS memory cell with two storage sites beneath the word gate in a NAND memory array.
It is yet an objective of the present invention to erase and program the storage sites using electron injection with FN tunneling and hot hole injection with band to band tunneling, respectively.
It is also yet an objective of the present invention to sequentially read odd (or even) storage sites on a column.
It is still yet an objective of the present invention to erase by block, program and read by storage cell.
A twin MONOS NAND memory array is produced where the memory cell contains two storage sites located below a word gate. Exclusive of column select, column voltages and word line voltages, no other controls are required to control memory operations. Unselected word lines are used to pass upper and lower column voltages to source and drain of the selected cell. The voltages on the source and drain of each cell along with the word gate voltage control the memory operations of each cell.
The twin MONOS memory cells are constructed on a P-type well by establishing blocks of SiO2 under which N-type regions were previously implanted. The N-type region comprises a lightly doped area within which is a heavily doped area. Silicon nitride deposited on the walls of the blocks and the area between blocks is masked by disposable sidewalls and etched to leave an xe2x80x9cLxe2x80x9d shaped element on adjacent sides of the blocks. The foot of the xe2x80x9cLxe2x80x9d silicon nitride shape that extends part way into the area between the SiO2 blocks is used as the storage sites for the twin MONOS memory cell. The SiN can be another insulator material different from the bottom and top insulator such as Ta2O5 and Zr O2 etc. The objective is to create trap sites for electron and hole storage at different insulator interfaces. A polysilicon layer is deposited in the region between blocks and over the xe2x80x9cLxe2x80x9d shaped silicon nitride. The polysilicon layer forms a word gate for the memory cell and is continuous over the width of the memory array becoming a word line. The diffusion areas under the SiO2 connect memory cells in a column together, providing a drain for one cell and a source for the adjacent cell.
Alternative fabrication method after defining the SiO2 block is also provided. ONO(Oxide-Nitride-Oxide) and polysilicon are subsequently deposited on the walls of the blocks. The area between blocks is masked by sidewall polysilicon and etched to leave an xe2x80x9cLxe2x80x9d shaped ONO element on adjacent sides of the blocks. The foot of the xe2x80x9cLxe2x80x9d shaped ONO that extends part way into the area between the SiO2 blocks is used as the storage sites for the twin MONOS memory cell. A gate oxide is grown on the exposed substrate between the L shapes. The oxide is also grown on the polysilicon sidewalls. A polysilicon layer is deposited in a trench between the polysilicon sidewalls and recessed to expose and remove the oxide on the polysilicon sidewalls. The polysilicon sidewall gates facing each other are connected by a tungsten stud process, which forms a word gate for the memory cell.
At the top and bottom of each column are upper and lower selector gates that select even or odd columns with voltages required to open or close the gates. With an upper and lower column voltage selected by the upper and lower selector gates, the unselected word lines bias the unselected memory cells to pass the upper and lower column voltages to the drain and source of the selected memory cell. Thus the combination of the voltage on the selected word line and the upper and lower column voltages passed by the unselected word lines, the selected storage site within a memory cell is read and programmed, and both storage sites of a block of memory cells are erased.
The memory density is doubled as compared to conventional floating gate devices because there are two storage elements under a single word gate. A shorter and thinner high voltage device is produced, which solves scaling and performance issues. Program and erase voltage reduction is possible as a result of not having to consider coupling ratios. Process simplicity is a result of to eliminating floating gate elements and by the method used to produce the twin storage sites. The nitride under the word gate can be continuous, but extra electrons are trapped at the middle of the channel if holes do not reach the center of the channel due to the short mean free path. This causes the center threshold to gradually get high after many program and erase cycles. This threshold instability due to uncontrolled electron charge at the middle of the channel is eliminated by separating the nitride layer at the middle and by providing charge trap free oxide in the middle of the channel. The controlled short storage elements allow a large threshold voltage fall off in forward read operations, and the large Vt fall off may extend the use of multi-level storage in the reverse read mode.